265625 MHz, and output 32-bit auto-negotiation data in a format shown in the following table at 312. Packets / Bytes 2. It provides the transceiver channel datapath description, clocking, and channel placement guidelines. XGXS converts bytes on an XGMII lane into a self clocked, serial, 8B/10B encoded data stream. The difference is the new one takes. System dimensions. By default, the PHY switches protocol during runtime, depending on the Ethernet speed (e. Kinda cool and nifty I think, and certainly some smarty pants bit hackers were involved designing the protocols. The Reconciliation Sublayer provides a mapping between the signals provided at the XGMII and the MAC/PLS service definition. The plurality of cross link multiplexers has a destination port coThe parallel transceiver ports 102a-102b can be XGMII parallel ports, for example, where the XGMII transceiver protocol is known to those skilled in the relevant art(s). 3. However, the XGXS is an older standard interface and is being absorbed into both MAC and PHY devices by silicon manufacturers. 4) PG029 Wireless Peak Cancellation Crest Factor Reduction (v6. Ethernet local area network operation is specified for selected speeds of operation from 1 Mb/s to 400 Gb/s using a common media access control (MAC) specification and management information base (MIB). (associated with MAC pacing). Full Quality of Service (QoS) support: Weighted random early discard (WRED). Vivado 2020. The method obtains the DIC variable value corresponding to the next frame of message before the current frame of message is sent, so that the DIC variable value corresponding to the. Additionally, for applications requiring 20 Gbps throughput, Intel FPGA's XAUI PHY solution can support DXAUI (4 x 6. 949962] NET: Registered protocol family 15 [ 2. SoCKit/ Cyclone V FPGA A. 3 2005 Standard. If is test the pcs/pma with 'pcs_loopback = 1' , everything works fine. XGMII 10 Gbit/s 32 Bit 74 156. The first input of data is encoded into four outputs of encoded data. Problem is, my fpga board only supports RGMII interface. Fundamentally the MII,SGMII,RGMII signals are for data that a MAC device converts to PHY. 3ae で規定された。 2002年に IEEE 802. XGMII, as defi ned in IEEE Std 802. SWAP C. IOD Features and User Modes. Analog Design: A Fully Differential Amplifier for 8-bit 10MS/s Pipeline ADCBuy VSC7301VF VITESSE , View the manufacturer, and stock, and datasheet pdf for the VSC7301VF at Jotrin Electronics. EPCS Interface for more information. 5 MHz. The data bus carries the MAC frame with the most significant byte occupying the least significant lane. Supports 10M, 100M, 1G, 2. TX Timing Diagrams. 3 media access control (MAC) and reconciliation sublayer (RS). It's exactly the same as the interface to a 10GBASE-R optical module. 3 protocol and MAC specification to an operating speedof 10 Gb/s. 5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core for Intel® Stratix® 10 devices (L- and H-tiles) implements the Ethernet protocol as defined in the IEEE 802. 3 Clause 46, is the main access to the 10G Ethernet physical layer. 4. 0 2 Freescale Semiconductor Figure 1 shows the connection between MPC8313E MAC and PHY with the support of SGMII. For Ethernet backplane applications, XGMII compliant 10GBASEKR_PHY soft IP is developed. The standard XLGMII or CGMII implementation. 958559] 8021q: 802. Inter-Packet Gap Generation and Insertion 4. The plurality of cross link multiplexers has a destination port coThe present application relates to a system and method for enabling lossless inter-packet gaps for lossy protocols. Avalon MM 3. イーサネットフレームの内部構造は、ieee 802. Contributions Appendix#It doesn’t implement supporting protocols as Address Resolution Protocol (ARP – translating IP addresses to MAC addresses), Dynamic Host Configuration Protocol (DHCP – often use to assign IP addresses dynamically) or Internet Control Message Protocol (ICMP – services like ping). Field of the Invention The present invention generally relates to serial de-serializer integrated circuits with multiple. /K/ or /R/ are neither part of RS protocol nor transported across the XGMII. 954432] Bridge firewalling registered [ 2. As Linux is running on the ARM system, a specific IMX547 driver is used. 14. 3ae として標準化された。. In the transmit direction, the 10GBASE-X PCS accepts packets from the PCS client on the XGMII. A communication device, method, and data transmission system are provided. Packets / Bytes 2. 10. The following features are supported in the 64b6xb: Fabric width is selectable. XAUI for more information. PTP Packet over UDP/IPv6. 1. An illustrative method is disclosed to include at least one data port configured to enable data transmission in compliance with a communication protocol. 2. These are. 3 protocol and MAC specification to an operating speedof 10 Gb/s. Neutral RD,hence current RD not affected by /R/’s insertion or deletion. Press protocol, as it is, unmodified, over a standard Ethernet connection, including fiber optics. Parameter Settings for the LL Ethernet 10G MAC Intel® FPGA IP Core 2. 3-2008 Choice of external XGMII or internal FPGA interface to PHY layer (internal interface only on Spartan®-6 devices) AXI4-Stream protocol , in both directions MDIO STA master interface to manage PHY layers Extremely customizable; trade , physical layer ( PHY ) device, for. Supported Ethernet speeds include 1, 2. 3 has the following abstraction layers: In this model SerDes will implement PMA/PMD sublayers, which is the logical sub-block responsible for interface initialization, encoding decoding, and clock alignment. Checksum calculation is optional for the UDP/IPv4 protocol. Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. For example, the 74 pins can transmit 36 data signals and receive 36 data. The 1G/2. Reload to refresh your session. 3 GMII IMPLEMENTATION ON THE C-5Attachment Unit Interface (XAUI) may optionally be used to extend the operational distance of the XGMII with reduced pin count (see Clause47). This module converts XGMII interface of XGMAC core. C. (2) The XGMII extender sublayer (XGXS) extends the distance of XGMII when used with XUAI and provides the data conversion between XGMII and XAUI. 2 interfaces, ten 1-Gigabit Ethernet ports and one 10-Gigabit Ethernet port with integrated MACs Software compatible with NP-2 and NP-1c Integrated Traffic Managers Traffic management for traffic on ingress and egress paths Work conserving and non-work conserving schedulersAMDGPU XGMI Support. Due to the continuously signaled nature of the underlying PMA, and the encoding performed by the PCS, the 10GBASE-X PCS maps XGMII data and control characters into a code-group stream. [0024]The four serial ports 104a-d can be XAUI serial ports,. Intel® Quartus® Prime Design Suite 19. (at least, and maybe others) is not > > > a part of XGMII protocol, I. Article Details. It also provides protocol specific implementation details and describes features such as transceiver reset and dynamic reconfiguration of transceiver channels and PLLs. 3ae. 3x Flow control functionality for support of Pause control frames. VMDS-10298. Avalon MM 3. If not, it shouldn't be documented this way in the standard. The received XGMII data are decoded to extract the auto-negotiation config words from auto-negotiation message. 5-gigabit Ethernet. Examples of protocol-specific PHYs include XAUI and Interlaken. Each direction is independent and contains a 32-bit. Unidirectional Feature 4. The latest Gigabit Ethernet switch devices with high port counts of 16-24 ports per chip have migrated towards SGMIIDocument Number ENG-46158 Revision Revision 1. 2. This line tells the driver to check the state of xGMI link. An Ethernet PHYsical layer device (PHY), which corresponds to Layer 1 of the OSI model, connects the. If not, it shouldn't be documented this way in the standard. for 1G it switches to SGMII). 12. Figure 49–4 depicts the relationship and mapping XGMII Mapping to Standard SDR XGMII Data 5. FAST MAC D. As far as I understand, of those 72 pins, only 64 are actually data, the remai. 10. XGMII stands for X(roman 10)-G-Media-Independant-Interface which is IEEE 802. 945496] NET: Registered protocol family 17 [ 2. 3-20220929P. that the XGMII definition must be expanded to include any extra characters defined in XGXS/XAUI. 3bz-2016 amending the XGMII specification to support operation at 2. 930855] NET: Registered protocol family 10 [ 2. A communication device, method, and data transmission system are provided. EPCS Interface for more information. 14. Thus, the mapping circuit 616 may map the protocol from the XGMII protocol back to 10M/100M/1G. Fundamentally the MII,SGMII,RGMII signals are for data that a MAC device converts to PHY. IEEE 802. SoCKit/ Cyclone V FPGA A. 10 Gigabit Ethernet Task Force XGMII Update La Jolla, CA 11-July-2000 Howard Frazier - Cisco Systems Goals and Assumptions Allow multiple PHY variations Provide a convenient partition for implementers Provide a standard interface between MAC and PHY Reference industry standard electrical specifications Interface Locations Management XAUI. 6. The XGMII interface, specified by IEEE 802. 8. Each XGMII port 102 can include 74 data pins, for example, operating at 1/10 the data rate of the serial ports 104. Dec. XGMII IV. Modules I. 5Gb/s, 5Gb/s, and 10Gb/s PHYs. 20. 5G, 5G, or 10GE data rates over a 10. Avalon ST to Avalon MM 1. USGMII and USXGMII Summary USGMII Specification The Universal Serial Gigabit Media Independent Interface (USGMII) is an. Universal SGMII and Univerisal XGMII MAC-PHY Interface Build next generation PHY and MACs with the ability to perform first auto-neg without PLL and SERDES parameters for 1G, 2. 3125 GHz Serial SFP+ MSA XAUI (“Zowie”) 10 Gbit/s 4 Lanes 16 3. On-chip OAM protocol processing offload Two SPI4. 1. The goal of the firmware is to apply multiple SiTCP cores as Gigabit protocol stack in the pixel detector’s readout system, then convert the data into 10-Gigabit proto-Fig. > * The XGXS /A/ character (at least, and maybe others) is not > a part of XGMII protocol, I believe. 3125 Gb/s link. I/O Features and Implementation. Configuration. • Two consecutive XGMII transfers (32 bits + 32 bits of data) are aggregated into a 64-bit data vector. A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. 23877. According to IEEE802. The XGMII may be used to attach the Ethernet MAC to its PHY. When the 10-Gigabit Ethernet MAC Core was. It is now typically used for on-chip connections. 2. 5, 10, 25, 40, 50, and 100 gigabits per second. 3125 Gbps serial single channel PHY over a backplane. Serial Data Interface 5. Both media access control (MAC) and physical coding sublayer/physical medium attachment (PCS/PMA) functions are included. The IEEE 802. 60/421,780, filed Oct. The XGMII consists of 32-bit data bus and 4-bit control bus operating at 312. An integrated circuit comprising a plurality of link layer controllers. The > Reconciliation Sublayer only generates /I/'s. XAUI PHY 1. 2. Note: 10GBASE-R is the single-channel protocol that. The parallel transceiver ports 102a,b can be XGMII parallel ports, for example, where the XGMII transceiver protocol is known to those skilled in the arts. 9. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a. No. 25 MHz Parallel IEEE standard XFI (“Ziffie”) 10 Gbit/s 1 Lane 4 10. The protocol-specific transceiver PHYs configure the PMA and PCS to implement a specific protocol. See the 5. 3ae で規定された。 2002年に IEEE 802. (MAC) core, which can be configured in XGMII and 10GBASE-R modes. 5GPII Word encoder/decoder –mapping between XGMII to Internal 2. A multi-port Serdes transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, oEmbodiments described herein provide a method for providing a compatible backplane operation mechanism for 2. On-chip FIFO 4. A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. 3 GMII IMPLEMENTATION ON THE C-5 Attachment Unit Interface (XAUI) may optionally be used to extend the operational distance of the XGMII with reduced pin count (see Clause47). of a MAC to an SFI port of a switch at board level (not via a DAC cable or such, but literally connecting ICs)?A crossbar may be coupled between a plurality of PHY devices configured to provide physical layer functions according to an Open Systems Interconnection, OSI, model and a plurality of MAC devices configured to provide data link layer functions according to the OSI model. 11. 3. Read clock. The data bus carries the MAC frame with the most significant byte occupying the least significant lane. URL Name. The IEEE 802. 25MHz (2エッジで312. 12/416,641, filed Apr. RGMII, XGMII, SGMII, or USXGMII. The first input of data is encoded into four outputs of encoded data. USXGMII. The full spec is defined in IEEE 802. MAC – PHY XLGMII or CGMII Interface. 125 GHz Serial. Protocol-Specific I/O Interfaces. XGMII Encapsulation 4. The first input of data is encoded into four outputs of encoded data. 1 - GMII to RGMII transform with using TEMAC Example Design. g. This interface operates at 322. It's exactly the same as the interface to a 10GBASE-R optical module. 25 Gbps). Packets / Bytes 2. 1G/10GbE GMII PCS Registers 5. x and XGMAC chip family. See the 5. 8. • XAUI Extender: This block is an XGMII extender to support the XAUI protocol through a FPGA IP MAC core in the FPGA fabric. Code replication/removal of lower rates onto the. 8. 4. Register Interface Signals 5. As far as I understand, of those 72 pins, only 64 are actually data, the remai. 4. This module receives 32-bit XGMII with data valid from RX 64/32 width adaptor at 322. S. Article Number. Clause 46. 5 Mbps)で動作する主信号 TXD/RXD 各32本と、制御フロー RXC/TXC 各4本が送受. Basically, you can think of the SFP+ to BASE-T module as a media converter - it receives 10GBASE-R on one end, and produces 10GBASE-T on the other end, and vise versa. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at is claimed is: 1. No. 5G/10G. XGMII signaling is based on the HSTL class 1 single-ended I/O standard, which has an electrical distance limitation of approximately 7 cm. 2. I/O Primitive. The plurality of cross link multiplexers has a destination port co10GbE XGMII TCP/IPv4 packet generator for Verilog. 3 Clause 37 Auto-Negotiation. FAST MAC D. Optional XGMII Extender XGMII 10 Gigabit Media Independent Interface 32 data (4 ‘lanes’ of 8 bits), 4 control and 1 DDR clock Medium XGMII XAUI XGMII XAUI 10 Gb/s Attachment Unit Interface 4 serial lanes @ 2. 5G/1G Multi-Speed Ethernet MACA cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The XGMII design in the 10-Gig MAC is available from CORE Generator. Document Revision History 802. That is, XGMII in and XGMII out. Actually - I should amend this answer - XGMII isn't the correct protocol, I think I'm thinking of 10GBASE-R. The first input of data is encoded into four outputs of encoded data. 6. In the context of 10GbE, I believe that LDPC (which is a type of FEC) is only used with 10GBase-T. Custom protocol. 25 Gbps) implementations on Stratix IV (GX and GT) FPGAs. 5Gb/s 8B/10B encoded - 3. Between the MAC and the PHY is the XGMII, or 10 Gigabit Media Independent Interface. 6. /K/ or /R/ are neither part of RS protocol nor transported across the XGMII. USXGMII Subsystem. On-chip FIFO 4. 1. 3ae で規定された。 72本の配線からなり、156. In a XAUI configuration, the transceiver channel data path is configured using soft PCS. -Developed the test plan document. It is also ready to be used with PHYs that support up to six speeds – 10 Gbps, 5 Gbps, 2. Both protocols should work between optical SFP+ modules that are controlled by the FPGA. Reconciliation Sublayer (RS) and XGMII. As such, CoaXPress-over-Fib-The main content of this module is to read out the data in the ram and package and send the data with the correct packet protocol type (UDP). See the 6. It consists of a physical coding sublayer (PCS) function and an embedded physical media attachment. XGMIIはMACとPHYの間に位置する。RSはMACのビットシリアルプロトコルをPHYのパラレルエンコーディングに適合させる。 XGMIIの使用は. • The SONET family of integrated, CMOS-based transceivers for OC-3 to OC-192 based applica-tions features multi-rate SerDes that incorporate MUX, de-MUX and CDR functions. Layer 2 protocol. FAST MAC D. 1 XGMII Controller Interface 3. References 7. 16. PLLs and Clock Networks 4. San Jose, CA 9513An automatic polarity swap is implemented in a communications system. XGMII, as defined in IEEE Std 802. Avalon ST to Avalon MM 1. #Databus#carries#the#MAC#frame#and#the#mostsignificantbyte#occupies#the#least significantlane. Otherwise you should favor the protocol that will work with other devices. XFI来源于XFP光模块标准的一部分，指的是连接ASIC芯片和XFP光模块的电气接口。. Interlaken 4. Contributions Appendix. Support to extend the IEEE 802. For 100M/1G GMII is mapped into XGMII in the Rate Adaptation/Replication block. 2/29/2016 Andra Radu - AMIQ Consulting Ionuț Ciocîrlan -AMIQ Consulting 27. Transceiver Configurations 4. 4. 6. 60/421,780, filed on Oct. Designed to meet the USXGMII specification EDCS-1467841 revision 1. 5. An optional physical instantiation of the PMA service interface has also been defined (see Clause 51). PHY is the physical media you attach to (Cat5/6 cable, or fiber, or WiFi). What is not symmetric is that the XGXS/XAUI/XGXS is not intended to sit "in the middle" of the XGMII so the notion of XAUI as a XGMII "extender" is not altogether appropriate for those individuals that can only envision an extender as something that goes in the middle. xGMI (inter-chip global memory interconnect) is a cable-capable version of AMD's Infinity Fabric interconnect. RS/XGMII • Upon reception of four local fault messages in 128 columns, the RS sets link_fault=Local Fault. 60/421,780, filed on Oct. 4. 1, 2009, which is a divisional of U. Historically, Ethernet has been used in local area networks (LANs. 5 MHz. XGMII Tx Data: While interfacing with 32-bit of the clock and xgmii_txd[63:32] is mapped to the negative edge. 5 MHz with TX/RX XGMII valid signal to reflect the data rate accordingly for the multiple Ethernet speed lower than 10G. 10Base-Te, 100Base-TX, 1000Base-T, 100Base-FX and 1000Base-X are supportedIntroduction. Compatible. Definitely not XGMII (32-bit DDR, was never really seen off-chip) or XAUI (4 lanes of 3. TX Timing Diagrams. 1G/10GbE Control and Status Interfaces 5. The XGMII protocol defines an 8 byte preamble for Ethernet Frames (consisting of one start character, six preamble bytes and one start of frame delimiter—FB 55 55 55 55 55 55 D5), a minimum of 64 and a maximum of 1518 payload data bytes (including CRC), one end of frame delimiter (FD) followed by a minimum of 12 interframe. > > XGXS, XAUI and XGMII are supposed to be PMD independent. PCI Express (PCIe)—Gen1, Gen2, and Gen3 4. 3bz-2016 amending the XGMII specification to support operation at 2. The core interfaces the Xilinx XAUI (IEEE 802. 64-bit XGMII for 10G (MGBASE-T). The communication device is further disclosed to include an Interpacket Gap (IPG) repair circuit configured to detect an IPG. S. XGMII protocol. 4. A communication device, a method and a data transmission system are provided. 7. Send Feedback. 254-1994 Fibre Channel. Dec. The design in CORE Generator contains necessary updates for Virtex-II and later devices. 0 Purpose The RGMII is intended to be an alternative to the IEEE802. Native transceiver PHY. 29, 2002, which is incorporated herein by reference. Example APB Interface. Y — GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FUS7782805B1 US11/349,212 US34921206A US7782805B1 US 7782805 B1 US7782805 B1 US 7782805B1 US 34921206 A US34921206 A US 34921206A US 7782805 B1 US7782805 B1 US 7782805B1 AuthorityUS20120072615A1 US13/305,207 US201113305207A US2012072615A1 US 20120072615 A1 US20120072615 A1 US 20120072615A1 US 201113305207 A US201113305207 A US 201113305207A US 2012072615 AFeatures. The XGMII design is now provided with the 10-Gig MAC Core in CORE Generator. * The XGXS /A/ character (at least, and maybe others) is not a part of XGMII protocol, I believe. You signed out in another tab or window. Table 1. III. 5G, 5G, or 10GE data rates over a 10. The generic nature of this interface facilitates mapping the CoaXPress signaling into the PCS/PMA. g. 802. 3 Ethernet Physical Layers. 7. Checksum calculation is mandatory for the UDP/IPv6 protocol. No. The Current driver assumes that AXI Stream FIFO is connected to the MAC TX Time stamp Stream interface at the design level. Software is only used for configuring the system, that means configuring the sensor and the GigE Vision IP. 3ae Task Force 13 Link Status Reporting and Initialization Status Message. 3ba standard. USXGMII is the only protocol which supports all speeds. • /T/-Maps to XGMII terminate control character. This PCS can interface with. 265625 MHz if the 10GBASE-R register mode is enabled. 15. Avalon MM 3. 3. 3. MII Interface Signals 5. Subscribe. TX FIFO E. XGMII Ethernet Verification IP is supported natively in . • EPCS: This block is a basic mode used to extend the SerDes for custom support access to the FPGA fabric. 1000BASE-X is based on the Physical Layer standards and this standard uses the same 8B/10B coding as Fibre Channel, a PMA sublayer compatible with speed-enhanced versions of the ANSI 10-bit serializer chip, and similar optical and. 3 is silent in this respect for 2. The generic nature of this interface facilitates mapping the CoaXPress signaling into the PCS. 3-2008 specification requires each 10GBASE. The Physical Coding Library provides support for the following types of errors: running disparity;. 4 11/18 Microsemi Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100Low Latency Ethernet 10G MAC User Guide. 5Gb/s, 5Gb/s, and 10Gb/s PHYs. This is probably 1000BASE-X. 3-2008 specification requires each 10GBASE-R link to support a 10 Gbps data rate at the XGMII interface and a 10. • The absence of fault messages for 128 columns resets link_fault=OK. Designed to meet the USXGMII specification EDCS-1467841 revision 1. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2. /K/ or /R/ are neither part of RS protocol nor transported across the XGMII. 5G/5G/10G Multirate Ethernet PHY Intel® FPGA IP Parameters. 25MHz for XGMII interface as shown below, The TX-FIFO now is working as a phase compensation mode. Hi @studded_seance (Member) ,. The 10GBASE-R PHY uses the XGMII interface to connect to the IEEE802. 8 Tb/s Multilayer Switch Features (continued) Buffering and traffic management: Integrated high-performance SmartBuffer memory for maximum burst absorption and service guarantees. 伝送路上のデータパケットとそのペイロードとしてのフレームは、バイナリデータで構成されている。イーサネットは最上位オクテットを先頭にしてデータを送信する。 ただし、各オクテット内では、最下位ビットが最初に送信される 。. However, if i set it to '0' to perform the described test it fails. November 6 -9, 2000, Tampa IEEE P802. Protocols and Transceiver PHY IP Support 4. Configuring SGMII Ethernet on the PowerQUICC™ MPC8313E Processor, Rev. 3 Clause 46 but we will save you the legalize parse time and explain it in pl USXGMII. 3ae. That is, XGMII in and XGMII out. Broadcom 56980-DS111 2 BCM56980 Data Sheet 12. For example, the 74 pins can transmit 36 data signals and receive 36 data. Both media access control (MAC) and physical coding sublayer/physical medium attachment (PCS/PMA) functions are included. XGMII Transmission 4. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The lossless IPG circuitry may include a lossless IPG insertion circuit and/or a lossless IPG removal circuit. What i want to do is i want to feed the PCS with xgmii_tx signals, connect the txn/txp to rxn/rxp respectively and monitor the xgmii_rx signals whether they are the same as xgmii_tx. 3ae standard protocols to a wire speed of 10 Gbps and expands the Ethernet application space to include WAN-compatible links. Apr 2, 2020 at 10:20. Each XGMII port 102 can include 74 data pins, for example, operating at 1/10 the data rate of the serial ports 104. (at least, and maybe others) is not > > > a part of XGMII protocol, I. But, on page 102 of the same manual, in the middle paragraph there is a statement, ” For 10GBASE-R, you must achieve 0 ppm of the frequency between the read clock of TX phase compensation FIFO (PCS data) and the write clock of TX. IP Core Generation. For example, the 74 pins can transmit 36 data signals and receive 36 data.